The trend in semiconductor devices is toward higher circuit density with higher numbers of transistors per device, lower operating voltages, and higher access speeds. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions.
Miniaturization of semiconductor devices necessitates a greater density of transistors to be placed in the same area by shrinking the size of individual components. The basic components of a transistor are a source and drain regions separated by a channel, where a gate is placed over the channel to control channel conductance. In such an arrangement, the width of the gate line is a limiting parameter of the channel width. The width of the gate line is often referred to as the critical dimension (CD) and influences the number of transistors that can be made to fit within a fixed area.
The most common technique for patterning each of the individual gate lines upon a semiconductor wafer is projection photo-lithography. A light-sensitive photoresist is placed upon a semiconductor wafer, which may have a device layer formed thereon. Light from a light source passes through a partially transparent pattern formed on a reticle (also known as a photomask), resulting in exposed and unexposed areas being formed on the photoresist, thereby transferring the pattern to the photoresist. A series of etching steps are then employed to transfer the pattern formed on the photoresist to a conductive layer that will become the individual transistor gates.